.amdgcn_target "amdgcn-amd-amdhsa--gfx1201" .amdhsa_code_object_version 6 .section .text._ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd,"axG",@progbits,_ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd,comdat .globl _ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd ; -- Begin function _ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd .p2align 8 .type _ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd,@function _ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd: ; @_ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd ; %bb.0: s_clause 0x1 s_load_b32 s2, s[0:1], 0x44 s_load_b128 s[4:7], s[0:1], 0x0 v_mov_b32_e32 v1, 0 s_wait_kmcnt 0x0 s_and_b32 s2, s2, 0xffff s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_mad_co_u64_u32 v[3:4], null, s2, ttmp9, v[0:1] s_mov_b32 s2, exec_lo v_lshrrev_b64 v[1:2], 5, v[3:4] s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_u64_e64 s[6:7], v[1:2] s_cbranch_execz .LBB0_19 ; %bb.1: v_mad_co_u64_u32 v[0:1], null, v1, 56, s[4:5] s_load_b128 s[4:7], s[0:1], 0x28 v_mad_co_u64_u32 v[1:2], null, v2, 56, v[1:2] global_load_b64 v[4:5], v[0:1], off offset:48 s_wait_kmcnt 0x0 v_max_num_f64_e64 v[8:9], s[4:5], s[4:5] s_wait_loadcnt 0x0 v_ceil_f64_e32 v[6:7], v[4:5] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_min_num_f64_e32 v[6:7], v[6:7], v[8:9] v_cvt_i32_f64_e32 v41, v[6:7] s_delay_alu instid0(VALU_DEP_1) v_cmp_lt_i32_e32 vcc_lo, -1, v41 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB0_19 ; %bb.2: s_clause 0x2 global_load_b128 v[6:9], v[0:1], off global_load_b128 v[17:20], v[0:1], off offset:16 global_load_b128 v[27:30], v[0:1], off offset:32 s_load_b64 s[4:5], s[0:1], 0x20 v_sub_nc_u32_e32 v44, 0, v41 s_load_b128 s[0:3], s[0:1], 0x10 v_and_b32_e32 v45, 31, v3 ; implicit-def: $vgpr49 ; implicit-def: $vgpr50 s_delay_alu instid0(VALU_DEP_2) v_mov_b32_e32 v48, v44 s_wait_kmcnt 0x0 s_ashr_i32 s9, s4, 31 s_mov_b32 s8, s4 s_ashr_i32 s11, s5, 31 s_add_nc_u64 s[12:13], s[8:9], 1 s_mov_b32 s10, s5 s_delay_alu instid0(SALU_CYCLE_1) s_lshl_b64 s[8:9], s[10:11], 1 s_ashr_i32 s10, s0, 31 s_or_b32 s8, s8, 1 s_wait_loadcnt 0x2 v_floor_f64_e32 v[10:11], v[8:9] v_floor_f64_e32 v[12:13], v[6:7] s_wait_loadcnt 0x0 v_mul_f64_e32 v[17:18], v[17:18], v[29:30] v_mul_f64_e32 v[19:20], v[19:20], v[29:30] v_mul_f64_e32 v[27:28], v[27:28], v[29:30] v_cvt_i32_f64_e32 v42, v[10:11] v_cvt_i32_f64_e32 v43, v[12:13] v_cvt_f64_i32_e32 v[13:14], s4 s_mov_b32 s4, 0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cvt_f64_i32_e32 v[0:1], v42 v_cvt_f64_i32_e32 v[11:12], v43 v_sub_nc_u32_e32 v46, 0, v43 v_xad_u32 v47, v43, -1, s0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_add_f64_e64 v[9:10], v[8:9], -v[0:1] v_add_f64_e64 v[0:1], v[6:7], -v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_f64_e32 v[6:7], v[9:10], v[13:14] v_mul_f64_e32 v[11:12], v[0:1], v[13:14] v_add_f64_e32 v[21:22], -0.5, v[0:1] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_floor_f64_e32 v[6:7], v[6:7] v_floor_f64_e32 v[11:12], v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_i32_f64_e32 v2, v[6:7] v_cvt_i32_f64_e32 v6, v[11:12] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_f64_i32_e32 v[7:8], v2 v_cvt_f64_i32_e32 v[15:16], v6 v_add_nc_u32_e32 v31, 1, v6 v_mul_lo_u32 v33, s13, v2 v_add_nc_u32_e32 v34, 1, v2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v32, 31, v31 v_ashrrev_i32_e32 v35, 31, v34 v_fma_f64 v[11:12], v[9:10], v[13:14], -v[7:8] v_fma_f64 v[13:14], v[0:1], v[13:14], -v[15:16] v_ashrrev_i32_e32 v7, 31, v6 v_ashrrev_i32_e32 v8, 31, v2 v_mul_f64_e32 v[15:16], v[4:5], v[4:5] v_mad_co_u64_u32 v[0:1], null, s12, v2, v[31:32] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_mad_co_u64_u32 v[4:5], null, s12, v2, v[6:7] v_mul_lo_u32 v8, s12, v8 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_mul_lo_u32 v38, v4, s11 v_mad_co_u64_u32 v[29:30], null, v4, s8, 0 v_add3_u32 v5, v33, v5, v8 v_add3_u32 v8, v33, v1, v8 v_mad_co_u64_u32 v[1:2], null, s12, v34, v[31:32] v_mad_co_u64_u32 v[31:32], null, v0, s8, 0 s_delay_alu instid0(VALU_DEP_4) v_mul_lo_u32 v37, v5, s8 v_mad_co_u64_u32 v[5:6], null, s12, v34, v[6:7] v_mul_lo_u32 v7, s12, v35 v_mul_lo_u32 v35, s13, v34 v_mul_lo_u32 v4, v8, s8 v_mul_lo_u32 v8, v0, s11 v_add3_u32 v30, v30, v38, v37 v_mad_co_u64_u32 v[33:34], null, v5, s8, 0 v_add3_u32 v6, v35, v6, v7 v_add3_u32 v0, v35, v2, v7 v_add_f64_e64 v[23:24], -v[11:12], 1.0 v_add_f64_e64 v[25:26], -v[13:14], 1.0 v_mad_co_u64_u32 v[35:36], null, v1, s8, 0 v_mul_lo_u32 v2, v6, s8 v_mul_lo_u32 v6, v5, s11 v_mul_lo_u32 v0, v0, s8 v_mul_lo_u32 v5, v1, s11 v_add3_u32 v32, v32, v8, v4 s_mov_b32 s11, s0 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) v_add3_u32 v34, v34, v6, v2 v_add3_u32 v36, v36, v5, v0 s_branch .LBB0_6 .LBB0_3: ; in Loop: Header=BB0_6 Depth=1 s_wait_alu depctr_sa_sdst(0) s_or_b32 exec_lo, exec_lo, s13 .LBB0_4: ; in Loop: Header=BB0_6 Depth=1 s_wait_alu depctr_sa_sdst(0) s_or_b32 exec_lo, exec_lo, s12 .LBB0_5: ; in Loop: Header=BB0_6 Depth=1 s_wait_alu depctr_sa_sdst(0) s_or_b32 exec_lo, exec_lo, s0 v_add_nc_u32_e32 v0, 1, v48 v_cmp_eq_u32_e32 vcc_lo, v48, v41 s_delay_alu instid0(VALU_DEP_2) v_mov_b32_e32 v48, v0 s_or_b32 s4, vcc_lo, s4 s_wait_alu depctr_sa_sdst(0) s_and_not1_b32 exec_lo, exec_lo, s4 s_cbranch_execz .LBB0_19 .LBB0_6: ; =>This Loop Header: Depth=1 ; Child Loop BB0_12 Depth 2 ; Child Loop BB0_13 Depth 3 ; Child Loop BB0_15 Depth 3 ; Child Loop BB0_17 Depth 3 v_add_nc_u32_e32 v2, v48, v42 s_delay_alu instid0(VALU_DEP_1) v_cmp_lt_i32_e32 vcc_lo, -1, v2 v_cmp_gt_i32_e64 s0, s1, v2 s_and_b32 s12, vcc_lo, s0 s_wait_alu depctr_sa_sdst(0) s_and_saveexec_b32 s0, s12 s_cbranch_execz .LBB0_5 ; %bb.7: ; in Loop: Header=BB0_6 Depth=1 v_cvt_f64_i32_e32 v[0:1], v48 s_mov_b32 s13, -1 s_mov_b32 s12, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64_e32 v[0:1], 0.5, v[0:1] v_add_f64_e64 v[0:1], v[0:1], -v[9:10] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[0:1], -v[0:1], v[0:1], v[15:16] v_cmpx_ngt_f64_e32 0, v[0:1] s_cbranch_execz .LBB0_9 ; %bb.8: ; in Loop: Header=BB0_6 Depth=1 v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[0:1] s_wait_alu depctr_va_vcc(0) v_cndmask_b32_e64 v3, 0, 0x100, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[0:1], v[0:1], v3 v_rsq_f64_e32 v[3:4], v[0:1] s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mul_f64_e32 v[5:6], v[0:1], v[3:4] v_mul_f64_e32 v[3:4], 0.5, v[3:4] v_fma_f64 v[7:8], -v[3:4], v[5:6], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6] v_fma_f64 v[3:4], v[3:4], v[7:8], v[3:4] v_fma_f64 v[7:8], -v[5:6], v[5:6], v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[5:6], v[7:8], v[3:4], v[5:6] v_fma_f64 v[7:8], -v[5:6], v[5:6], v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_fma_f64 v[3:4], v[7:8], v[3:4], v[5:6] v_cndmask_b32_e64 v5, 0, 0xffffff80, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x260 v_ldexp_f64 v[3:4], v[3:4], v5 s_wait_alu depctr_va_vcc(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v1, v4, v1 :: v_dual_cndmask_b32 v0, v3, v0 v_add_f64_e64 v[3:4], v[21:22], -v[0:1] v_add_f64_e32 v[0:1], v[21:22], v[0:1] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ceil_f64_e32 v[3:4], v[3:4] v_floor_f64_e32 v[0:1], v[0:1] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_i32_f64_e32 v3, v[3:4] v_cvt_i32_f64_e32 v0, v[0:1] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_max_i32_e32 v50, v3, v44 v_min_i32_e32 v49, v41, v0 s_delay_alu instid0(VALU_DEP_1) v_cmp_gt_i32_e32 vcc_lo, v50, v49 s_or_not1_b32 s13, vcc_lo, exec_lo .LBB0_9: ; in Loop: Header=BB0_6 Depth=1 s_wait_alu depctr_sa_sdst(0) s_or_b32 exec_lo, exec_lo, s12 s_xor_b32 s13, s13, -1 s_wait_alu depctr_sa_sdst(0) s_and_saveexec_b32 s12, s13 s_cbranch_execz .LBB0_4 ; %bb.10: ; in Loop: Header=BB0_6 Depth=1 v_max_i32_e32 v50, v50, v46 v_min_i32_e32 v49, v49, v47 s_mov_b32 s13, exec_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_nc_u32_e32 v51, v50, v45 v_cmpx_le_i32_e64 v51, v49 s_cbranch_execz .LBB0_3 ; %bb.11: ; in Loop: Header=BB0_6 Depth=1 v_add_nc_u32_e32 v5, s5, v48 s_mov_b32 s14, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v6, 31, v5 v_add_co_u32 v0, vcc_lo, v29, v5 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v3, null, v30, v6, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_mul_lo_u32 v7, v0, s9 v_mad_co_u64_u32 v[0:1], null, v0, s8, 0 v_mul_lo_u32 v37, v3, s8 v_add_co_u32 v4, vcc_lo, v31, v5 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v8, null, v32, v6, vcc_lo v_add_co_u32 v38, vcc_lo, v33, v5 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v39, null, v34, v6, vcc_lo v_mul_lo_u32 v40, v4, s9 v_mad_co_u64_u32 v[3:4], null, v4, s8, 0 v_mul_lo_u32 v8, v8, s8 v_add3_u32 v1, v1, v7, v37 v_add_co_u32 v7, vcc_lo, v35, v5 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v52, null, v36, v6, vcc_lo v_mul_lo_u32 v39, v39, s8 v_mul_lo_u32 v37, v38, s9 v_mad_co_u64_u32 v[5:6], null, v38, s8, 0 v_lshlrev_b64_e32 v[0:1], 2, v[0:1] v_add3_u32 v4, v4, v40, v8 v_mul_lo_u32 v40, v52, s8 v_mul_lo_u32 v54, v7, s9 v_mad_co_u64_u32 v[7:8], null, v7, s8, 0 v_add_co_u32 v52, vcc_lo, s2, v0 v_add3_u32 v6, v6, v37, v39 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v53, null, s3, v1, vcc_lo v_lshlrev_b64_e32 v[0:1], 2, v[3:4] v_add3_u32 v8, v8, v54, v40 v_lshlrev_b64_e32 v[37:38], 2, v[5:6] v_mad_co_u64_u32 v[4:5], null, v2, s11, 0 s_delay_alu instid0(VALU_DEP_4) v_add_co_u32 v54, vcc_lo, s2, v0 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v55, null, s3, v1, vcc_lo v_lshlrev_b64_e32 v[0:1], 2, v[7:8] v_add_co_u32 v56, vcc_lo, s2, v37 v_mad_co_u64_u32 v[5:6], null, v2, s10, v[5:6] s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v57, null, s3, v38, vcc_lo s_delay_alu instid0(VALU_DEP_4) v_add_co_u32 v58, vcc_lo, s2, v0 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v59, null, s3, v1, vcc_lo .LBB0_12: ; Parent Loop BB0_6 Depth=1 ; => This Loop Header: Depth=2 ; Child Loop BB0_13 Depth 3 ; Child Loop BB0_15 Depth 3 ; Child Loop BB0_17 Depth 3 v_add_nc_u32_e32 v0, s5, v51 s_mov_b32 s15, 0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ashrrev_i32_e32 v1, 31, v0 v_lshlrev_b64_e32 v[0:1], 2, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_co_u32 v2, vcc_lo, v58, v0 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v3, null, v59, v1, vcc_lo global_load_b32 v37, v[2:3], off v_add_co_u32 v2, vcc_lo, v54, v0 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v3, null, v55, v1, vcc_lo v_add_co_u32 v6, vcc_lo, v56, v0 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v7, null, v57, v1, vcc_lo s_clause 0x1 global_load_b32 v38, v[2:3], off global_load_b32 v39, v[6:7], off v_add_co_u32 v0, vcc_lo, v52, v0 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v1, null, v53, v1, vcc_lo global_load_b32 v60, v[0:1], off v_add_nc_u32_e32 v0, v51, v43 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_ashrrev_i32_e32 v1, 31, v0 v_add_co_u32 v0, vcc_lo, v4, v0 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v1, null, v5, v1, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_co_u64_u32 v[6:7], null, v0, 24, s[6:7] v_mad_co_u64_u32 v[7:8], null, v1, 24, v[7:8] global_load_b64 v[2:3], v[6:7], off s_wait_loadcnt 0x4 v_cvt_f64_f32_e32 v[0:1], v37 s_wait_loadcnt 0x3 v_cvt_f64_f32_e32 v[37:38], v38 s_wait_loadcnt 0x2 v_cvt_f64_f32_e32 v[39:40], v39 s_wait_loadcnt 0x1 v_cvt_f64_f32_e32 v[60:61], v60 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_mul_f64_e32 v[0:1], v[13:14], v[0:1] v_mul_f64_e32 v[37:38], v[13:14], v[37:38] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_fma_f64 v[0:1], v[25:26], v[39:40], v[0:1] v_fma_f64 v[37:38], v[25:26], v[60:61], v[37:38] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64_e32 v[0:1], v[11:12], v[0:1] v_fma_f64 v[37:38], v[23:24], v[37:38], v[0:1] s_delay_alu instid0(VALU_DEP_1) v_mul_f64_e32 v[39:40], v[17:18], v[37:38] .LBB0_13: ; Parent Loop BB0_6 Depth=1 ; Parent Loop BB0_12 Depth=2 ; => This Inner Loop Header: Depth=3 s_wait_loadcnt 0x0 s_delay_alu instid0(VALU_DEP_1) v_add_f64_e32 v[0:1], v[2:3], v[39:40] global_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV s_wait_loadcnt 0x0 v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3] v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 s_or_b32 s15, vcc_lo, s15 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s15 s_cbranch_execnz .LBB0_13 ; %bb.14: ; in Loop: Header=BB0_12 Depth=2 s_or_b32 exec_lo, exec_lo, s15 global_load_b64 v[2:3], v[6:7], off offset:8 v_mul_f64_e32 v[39:40], v[19:20], v[37:38] s_mov_b32 s15, 0 .LBB0_15: ; Parent Loop BB0_6 Depth=1 ; Parent Loop BB0_12 Depth=2 ; => This Inner Loop Header: Depth=3 s_wait_loadcnt 0x0 s_delay_alu instid0(VALU_DEP_1) v_add_f64_e32 v[0:1], v[2:3], v[39:40] global_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3], off offset:8 th:TH_ATOMIC_RETURN scope:SCOPE_DEV s_wait_loadcnt 0x0 v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3] v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 s_or_b32 s15, vcc_lo, s15 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s15 s_cbranch_execnz .LBB0_15 ; %bb.16: ; in Loop: Header=BB0_12 Depth=2 s_or_b32 exec_lo, exec_lo, s15 global_load_b64 v[2:3], v[6:7], off offset:16 v_mul_f64_e32 v[37:38], v[27:28], v[37:38] s_mov_b32 s15, 0 .LBB0_17: ; Parent Loop BB0_6 Depth=1 ; Parent Loop BB0_12 Depth=2 ; => This Inner Loop Header: Depth=3 s_wait_loadcnt 0x0 s_delay_alu instid0(VALU_DEP_1) v_add_f64_e32 v[0:1], v[2:3], v[37:38] global_atomic_cmpswap_b64 v[0:1], v[6:7], v[0:3], off offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_DEV s_wait_loadcnt 0x0 v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3] v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0 s_or_b32 s15, vcc_lo, s15 s_delay_alu instid0(SALU_CYCLE_1) s_and_not1_b32 exec_lo, exec_lo, s15 s_cbranch_execnz .LBB0_17 ; %bb.18: ; in Loop: Header=BB0_12 Depth=2 s_or_b32 exec_lo, exec_lo, s15 v_add_nc_u32_e32 v51, 32, v51 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) v_cmp_gt_i32_e32 vcc_lo, v51, v49 s_or_b32 s14, vcc_lo, s14 s_and_not1_b32 exec_lo, exec_lo, s14 s_cbranch_execnz .LBB0_12 s_branch .LBB0_3 .LBB0_19: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 312 .amdhsa_user_sgpr_count 2 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 62 .amdhsa_next_free_sgpr 16 .amdhsa_reserve_vcc 1 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 1 .amdhsa_inst_pref_size 17 .amdhsa_round_robin_scheduling 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd,"axG",@progbits,_ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd,comdat .Lfunc_end0: .size _ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd, .Lfunc_end0-_ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd ; -- End function .set _ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd.num_vgpr, 62 .set _ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd.num_agpr, 0 .set _ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd.numbered_sgpr, 16 .set _ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd.num_named_barrier, 0 .set _ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd.private_seg_size, 0 .set _ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd.uses_vcc, 1 .set _ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd.uses_flat_scratch, 0 .set _ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd.has_dyn_sized_stack, 0 .set _ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd.has_recursion, 0 .set _ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd.has_indirect_call, 0 .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 2056 ; TotalNumSgprs: 18 ; NumVgprs: 62 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 7 ; NumSGPRsForWavesPerEU: 18 ; NumVGPRsForWavesPerEU: 62 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 2 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .section .text._ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi,"axG",@progbits,_ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi,comdat .globl _ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi ; -- Begin function _ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi .p2align 8 .type _ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi,@function _ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi: ; @_ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi ; %bb.0: s_clause 0x1 s_load_b32 s8, s[0:1], 0x3c s_load_b128 s[4:7], s[0:1], 0x0 v_mov_b32_e32 v1, 0 s_wait_kmcnt 0x0 s_and_b32 s2, s8, 0xffff s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) v_mad_co_u64_u32 v[14:15], null, s2, ttmp9, v[0:1] s_mov_b32 s2, exec_lo v_lshrrev_b64 v[8:9], 5, v[14:15] s_delay_alu instid0(VALU_DEP_1) v_cmpx_gt_u64_e64 s[6:7], v[8:9] s_cbranch_execz .LBB1_10 ; %bb.1: v_mad_co_u64_u32 v[4:5], null, v8, 56, s[4:5] s_clause 0x2 s_load_b128 s[4:7], s[0:1], 0x18 s_load_b64 s[2:3], s[0:1], 0x10 s_load_b64 s[0:1], s[0:1], 0x28 v_and_b32_e32 v14, 31, v14 s_delay_alu instid0(VALU_DEP_2) v_mad_co_u64_u32 v[5:6], null, v9, 56, v[5:6] s_clause 0x1 global_load_b128 v[15:18], v[4:5], off global_load_b64 v[10:11], v[4:5], off offset:48 s_wait_kmcnt 0x0 v_max_num_f64_e64 v[12:13], s[4:5], s[4:5] s_mov_b32 s4, exec_lo s_wait_loadcnt 0x1 v_floor_f64_e32 v[1:2], v[15:16] v_floor_f64_e32 v[6:7], v[17:18] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_i32_f64_e32 v1, v[1:2] v_cvt_i32_f64_e32 v2, v[6:7] s_wait_loadcnt 0x0 v_ceil_f64_e32 v[6:7], v[10:11] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_cvt_f64_i32_e32 v[19:20], v1 v_cvt_f64_i32_e32 v[21:22], v2 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_min_num_f64_e32 v[23:24], v[6:7], v[12:13] v_add_f64_e64 v[12:13], v[15:16], -v[19:20] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_f64_e64 v[6:7], v[17:18], -v[21:22] v_cvt_i32_f64_e32 v3, v[23:24] v_cmpx_eq_u32_e32 0, v14 s_cbranch_execz .LBB1_3 ; %bb.2: s_clause 0x1 global_load_b128 v[15:18], v[4:5], off offset:32 global_load_b128 v[19:22], v[4:5], off offset:16 v_cvt_f64_i32_e32 v[4:5], s2 s_ashr_i32 s11, s2, 31 s_mov_b32 s10, s2 s_lshl_b32 s2, s3, 1 s_add_nc_u64 s[10:11], s[10:11], 1 s_wait_alu depctr_sa_sdst(0) s_or_b32 s2, s2, 1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_mul_f64_e32 v[23:24], v[12:13], v[4:5] v_mul_f64_e32 v[25:26], v[6:7], v[4:5] v_floor_f64_e32 v[23:24], v[23:24] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_floor_f64_e32 v[25:26], v[25:26] v_cvt_i32_f64_e32 v23, v[23:24] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_i32_f64_e32 v29, v[25:26] v_cvt_f64_i32_e32 v[25:26], v23 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3) v_cvt_f64_i32_e32 v[27:28], v29 v_ashrrev_i32_e32 v30, 31, v29 v_ashrrev_i32_e32 v24, 31, v23 v_mul_lo_u32 v35, s11, v29 s_ashr_i32 s11, s3, 31 v_mul_lo_u32 v36, s10, v30 s_delay_alu instid0(VALU_DEP_3) v_mad_co_u64_u32 v[33:34], null, s10, v29, v[23:24] s_mov_b32 s10, s3 v_fma_f64 v[23:24], v[12:13], v[4:5], -v[25:26] v_fma_f64 v[25:26], v[6:7], v[4:5], -v[27:28] s_wait_alu depctr_sa_sdst(0) v_mad_co_u64_u32 v[4:5], null, v33, s2, s[10:11] s_wait_loadcnt 0x1 v_mul_f64_e32 v[31:32], v[17:18], v[15:16] s_wait_loadcnt 0x0 v_mul_f64_e32 v[27:28], v[17:18], v[19:20] v_mul_f64_e32 v[29:30], v[17:18], v[21:22] v_add3_u32 v15, v35, v34, v36 v_mul_lo_u32 v16, v33, s11 v_mul_lo_u32 v17, v4, s11 v_mad_co_u64_u32 v[21:22], null, v4, s2, s[10:11] s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v15, v15, s2 v_add3_u32 v5, v15, v5, v16 v_lshlrev_b64_e32 v[15:16], 6, v[8:9] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_mul_lo_u32 v18, v5, s2 v_add_co_u32 v4, vcc_lo, s6, v15 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_add_co_ci_u32_e64 v5, null, s7, v16, vcc_lo v_add3_u32 v22, v18, v22, v17 s_clause 0x3 global_store_b96 v[4:5], v[1:3], off global_store_b128 v[4:5], v[21:24], off offset:16 global_store_b128 v[4:5], v[25:28], off offset:32 global_store_b128 v[4:5], v[29:32], off offset:48 .LBB1_3: s_wait_alu depctr_sa_sdst(0) s_or_b32 exec_lo, exec_lo, s4 s_lshl_b32 s2, s3, 1 s_wait_alu depctr_sa_sdst(0) v_cmp_ge_i32_e32 vcc_lo, s2, v14 s_and_b32 exec_lo, exec_lo, vcc_lo s_cbranch_execz .LBB1_10 ; %bb.4: v_mul_f64_e32 v[1:2], v[10:11], v[10:11] v_mad_co_u64_u32 v[10:11], null, v8, s2, v[8:9] v_add_f64_e32 v[4:5], -0.5, v[12:13] s_mul_i32 s4, ttmp9, s8 s_sub_co_i32 s3, 0, s3 s_wait_alu depctr_sa_sdst(0) v_add_nc_u16 v0, s4, v0 s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_co_u64_u32 v[11:12], null, v9, s2, v[11:12] v_and_b32_e32 v0, 31, v0 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshlrev_b32_e32 v0, 3, v0 v_lshlrev_b64_e32 v[8:9], 3, v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_co_u32 v0, vcc_lo, v8, v0 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v8, null, 0, v9, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_co_u32 v9, vcc_lo, s0, v0 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v10, null, s1, v8, vcc_lo v_sub_nc_u32_e32 v0, 0, v3 s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_add_co_u32 v8, vcc_lo, v9, 4 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v9, null, 0, v10, vcc_lo s_mov_b32 s1, 0 s_branch .LBB1_7 .LBB1_5: ; in Loop: Header=BB1_7 Depth=1 s_wait_alu depctr_sa_sdst(0) s_or_b32 exec_lo, exec_lo, s4 .LBB1_6: ; in Loop: Header=BB1_7 Depth=1 s_wait_alu depctr_sa_sdst(0) s_or_b32 exec_lo, exec_lo, s0 v_add_nc_u32_e32 v14, 32, v14 global_store_b64 v[8:9], v[10:11], off offset:-4 v_add_co_u32 v8, s0, 0x100, v8 s_wait_alu depctr_va_sdst(0) v_add_co_ci_u32_e64 v9, null, 0, v9, s0 v_cmp_lt_i32_e32 vcc_lo, s2, v14 s_or_b32 s1, vcc_lo, s1 s_wait_alu depctr_sa_sdst(0) s_and_not1_b32 exec_lo, exec_lo, s1 s_cbranch_execz .LBB1_10 .LBB1_7: ; =>This Inner Loop Header: Depth=1 v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v12, s3, v14 v_mov_b32_e32 v10, 1 s_delay_alu instid0(VALU_DEP_2) v_cmp_ge_i32_e32 vcc_lo, v12, v0 v_cmp_le_i32_e64 s0, v12, v3 s_and_b32 s4, vcc_lo, s0 s_wait_alu depctr_sa_sdst(0) s_and_saveexec_b32 s0, s4 s_cbranch_execz .LBB1_6 ; %bb.8: ; in Loop: Header=BB1_7 Depth=1 v_cvt_f64_i32_e32 v[10:11], v12 s_mov_b32 s4, exec_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_add_f64_e32 v[10:11], 0.5, v[10:11] v_add_f64_e64 v[10:11], v[10:11], -v[6:7] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[12:13], -v[10:11], v[10:11], v[1:2] v_dual_mov_b32 v10, 1 :: v_dual_mov_b32 v11, 0 v_cmpx_ngt_f64_e32 0, v[12:13] s_cbranch_execz .LBB1_5 ; %bb.9: ; in Loop: Header=BB1_7 Depth=1 v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[12:13] s_wait_alu depctr_va_vcc(0) v_cndmask_b32_e64 v10, 0, 0x100, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_ldexp_f64 v[10:11], v[12:13], v10 v_rsq_f64_e32 v[12:13], v[10:11] s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mul_f64_e32 v[15:16], v[10:11], v[12:13] v_mul_f64_e32 v[12:13], 0.5, v[12:13] v_fma_f64 v[17:18], -v[12:13], v[15:16], 0.5 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16] v_fma_f64 v[12:13], v[12:13], v[17:18], v[12:13] v_fma_f64 v[17:18], -v[15:16], v[15:16], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_fma_f64 v[15:16], v[17:18], v[12:13], v[15:16] v_fma_f64 v[17:18], -v[15:16], v[15:16], v[10:11] s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) v_fma_f64 v[12:13], v[17:18], v[12:13], v[15:16] v_cndmask_b32_e64 v15, 0, 0xffffff80, vcc_lo v_cmp_class_f64_e64 vcc_lo, v[10:11], 0x260 v_ldexp_f64 v[12:13], v[12:13], v15 s_wait_alu depctr_va_vcc(0) s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_dual_cndmask_b32 v11, v13, v11 :: v_dual_cndmask_b32 v10, v12, v10 v_add_f64_e64 v[12:13], v[4:5], -v[10:11] v_add_f64_e32 v[10:11], v[4:5], v[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_ceil_f64_e32 v[12:13], v[12:13] v_floor_f64_e32 v[10:11], v[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_cvt_i32_f64_e32 v12, v[12:13] v_cvt_i32_f64_e32 v11, v[10:11] s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) v_max_i32_e32 v10, v12, v0 v_min_i32_e32 v11, v3, v11 s_branch .LBB1_5 .LBB1_10: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 304 .amdhsa_user_sgpr_count 2 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 37 .amdhsa_next_free_sgpr 12 .amdhsa_reserve_vcc 1 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 1 .amdhsa_inst_pref_size 10 .amdhsa_round_robin_scheduling 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi,"axG",@progbits,_ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi,comdat .Lfunc_end1: .size _ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi, .Lfunc_end1-_ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi ; -- End function .set _ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi.num_vgpr, 37 .set _ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi.num_agpr, 0 .set _ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi.numbered_sgpr, 12 .set _ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi.num_named_barrier, 0 .set _ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi.private_seg_size, 0 .set _ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi.uses_vcc, 1 .set _ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi.uses_flat_scratch, 0 .set _ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi.has_dyn_sized_stack, 0 .set _ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi.has_recursion, 0 .set _ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi.has_indirect_call, 0 .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1172 ; TotalNumSgprs: 14 ; NumVgprs: 37 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 4 ; NumSGPRsForWavesPerEU: 14 ; NumVGPRsForWavesPerEU: 37 ; Occupancy: 16 ; WaveLimiterHint : 0 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 2 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .section .text._ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_,"axG",@progbits,_ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_,comdat .globl _ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_ ; -- Begin function _ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_ .p2align 8 .type _ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_,@function _ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_: ; @_ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_ ; %bb.0: s_clause 0x1 s_load_b128 s[20:23], s[0:1], 0x20 s_load_b256 s[4:11], s[0:1], 0x0 s_mov_b32 s34, ttmp9 s_mov_b32 s35, 0 v_mov_b32_e32 v9, 0 v_mov_b32_e32 v10, 0 s_wait_kmcnt 0x0 s_cvt_f32_u32 s2, s21 s_delay_alu instid0(SALU_CYCLE_3) v_rcp_iflag_f32_e32 v1, s2 s_lshl_b64 s[2:3], s[34:35], 4 s_wait_alu depctr_sa_sdst(0) s_add_nc_u64 s[2:3], s[10:11], s[2:3] s_load_b128 s[24:27], s[2:3], 0x0 s_sub_co_i32 s3, 0, s21 s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_2) v_readfirstlane_b32 s2, v1 s_mul_f32 s2, s2, 0x4f7ffffe s_wait_alu depctr_sa_sdst(0) s_cvt_u32_f32 s2, s2 s_wait_alu depctr_sa_sdst(0) s_delay_alu instid0(SALU_CYCLE_2) s_mul_i32 s3, s3, s2 s_wait_alu depctr_sa_sdst(0) s_mul_hi_u32 s3, s2, s3 s_wait_alu depctr_sa_sdst(0) s_add_co_i32 s2, s2, s3 s_wait_kmcnt 0x0 s_wait_alu depctr_sa_sdst(0) s_mul_hi_u32 s2, s24, s2 s_wait_alu depctr_sa_sdst(0) s_mul_i32 s3, s2, s21 s_add_co_i32 s10, s2, 1 s_wait_alu depctr_sa_sdst(0) s_sub_co_i32 s3, s24, s3 s_wait_alu depctr_sa_sdst(0) s_sub_co_i32 s11, s3, s21 s_cmp_ge_u32 s3, s21 s_cselect_b32 s2, s10, s2 s_cselect_b32 s3, s11, s3 s_wait_alu depctr_sa_sdst(0) s_add_co_i32 s10, s2, 1 s_cmp_ge_u32 s3, s21 s_cselect_b32 s2, s10, s2 s_abs_i32 s3, s20 s_wait_alu depctr_sa_sdst(0) s_cvt_f32_u32 s10, s3 s_sub_co_i32 s11, 0, s3 s_delay_alu instid0(SALU_CYCLE_2) | instskip(NEXT) | instid1(TRANS32_DEP_1) v_rcp_iflag_f32_e32 v1, s10 v_readfirstlane_b32 s10, v1 s_mul_f32 s10, s10, 0x4f7ffffe s_wait_alu depctr_sa_sdst(0) s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_2) s_cvt_u32_f32 s10, s10 s_wait_alu depctr_sa_sdst(0) s_mul_i32 s11, s11, s10 s_wait_alu depctr_sa_sdst(0) s_mul_hi_u32 s11, s10, s11 s_wait_alu depctr_sa_sdst(0) s_add_co_i32 s10, s10, s11 s_wait_alu depctr_sa_sdst(0) v_mul_hi_u32 v1, v0, s10 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v2, v1, s3 v_sub_nc_u32_e32 v2, v0, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v4, s3, v2 v_cmp_le_u32_e32 vcc_lo, s3, v2 v_dual_cndmask_b32 v2, v2, v4 :: v_dual_add_nc_u32 v3, 1, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_dual_cndmask_b32 v1, v1, v3 :: v_dual_mov_b32 v4, 0 v_mov_b32_e32 v5, 0 v_cmp_le_u32_e32 vcc_lo, s3, v2 s_delay_alu instid0(VALU_DEP_3) v_add_nc_u32_e32 v3, 1, v1 s_mul_i32 s3, s2, s21 s_ashr_i32 s21, s20, 31 s_wait_alu depctr_sa_sdst(0) s_sub_co_i32 s3, s24, s3 s_wait_alu depctr_va_vcc(0) v_cndmask_b32_e32 v1, v1, v3, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v1, s21, v1 v_subrev_nc_u32_e32 v1, s21, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v2, v1, s20 v_sub_nc_u32_e32 v2, v0, v2 s_delay_alu instid0(VALU_DEP_1) v_mad_co_u64_u32 v[6:7], null, s2, s20, v[1:2] s_wait_alu depctr_sa_sdst(0) v_mad_co_u64_u32 v[7:8], null, s3, s20, v[2:3] v_mov_b32_e32 v2, 0 v_mov_b32_e32 v3, 0 v_mov_b32_e32 v1, 0 v_cmp_gt_i32_e32 vcc_lo, s23, v6 v_cmp_gt_i32_e64 s2, s22, v7 s_and_b32 s23, s2, vcc_lo s_cmp_lg_u32 s26, 0 s_cselect_b32 s2, -1, 0 s_wait_alu depctr_sa_sdst(0) s_and_b32 s2, s23, s2 s_wait_alu depctr_sa_sdst(0) s_and_saveexec_b32 s3, s2 s_cbranch_execz .LBB2_9 ; %bb.1: s_load_b128 s[28:31], s[0:1], 0x30 v_mov_b32_e32 v2, 0 v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0 v_mov_b32_e32 v9, 0 v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v10, 0 s_mov_b32 s24, s25 s_wait_kmcnt 0x0 s_lshl_b32 s2, s31, 1 s_add_co_i32 s14, s30, 1 s_wait_alu depctr_sa_sdst(0) s_or_b32 s10, s2, 1 s_add_co_i32 s16, s30, 2 s_wait_alu depctr_sa_sdst(0) s_ashr_i32 s11, s10, 31 s_ashr_i32 s15, s14, 31 s_wait_alu depctr_sa_sdst(0) s_mul_u64 s[12:13], s[10:11], s[10:11] s_ashr_i32 s17, s16, 31 s_mul_u64 s[14:15], s[12:13], s[14:15] s_mul_u64 s[16:17], s[12:13], s[16:17] s_ashr_i32 s37, s31, 31 s_mov_b32 s36, s31 s_lshl_b64 s[30:31], s[12:13], 2 s_lshl_b64 s[38:39], s[14:15], 2 s_lshl_b64 s[40:41], s[16:17], 2 s_branch .LBB2_5 .LBB2_2: ; in Loop: Header=BB2_5 Depth=1 s_or_b32 exec_lo, exec_lo, s33 .LBB2_3: ; in Loop: Header=BB2_5 Depth=1 s_delay_alu instid0(SALU_CYCLE_1) s_or_b32 exec_lo, exec_lo, s25 .LBB2_4: ; in Loop: Header=BB2_5 Depth=1 s_wait_alu depctr_sa_sdst(0) s_or_b32 exec_lo, exec_lo, s2 s_add_co_i32 s26, s26, -1 s_add_co_i32 s24, s24, 1 s_cmp_lg_u32 s26, 0 s_cbranch_scc0 .LBB2_9 .LBB2_5: ; =>This Inner Loop Header: Depth=1 s_mov_b32 s25, s35 s_delay_alu instid0(SALU_CYCLE_1) s_lshl_b64 s[12:13], s[24:25], 2 s_wait_alu depctr_sa_sdst(0) s_add_nc_u64 s[12:13], s[8:9], s[12:13] s_load_b32 s34, s[12:13], 0x0 s_wait_kmcnt 0x0 s_lshl_b64 s[12:13], s[34:35], 6 s_wait_alu depctr_sa_sdst(0) s_add_nc_u64 s[42:43], s[4:5], s[12:13] s_load_b96 s[12:14], s[42:43], 0x0 s_wait_kmcnt 0x0 v_subrev_nc_u32_e32 v8, s13, v6 s_sub_co_i32 s2, 0, s14 s_wait_alu depctr_sa_sdst(0) s_delay_alu instid0(VALU_DEP_1) v_cmp_le_i32_e32 vcc_lo, s2, v8 v_cmp_ge_i32_e64 s2, s14, v8 s_and_b32 s13, vcc_lo, s2 s_wait_alu depctr_sa_sdst(0) s_and_saveexec_b32 s2, s13 s_cbranch_execz .LBB2_4 ; %bb.6: ; in Loop: Header=BB2_5 Depth=1 s_mul_u64 s[14:15], s[34:35], s[10:11] v_ashrrev_i32_e32 v12, 31, v8 s_wait_alu depctr_sa_sdst(0) s_add_nc_u64 s[14:15], s[14:15], s[36:37] s_mov_b32 s25, exec_lo s_wait_alu depctr_sa_sdst(0) v_add_co_u32 v11, vcc_lo, s14, v8 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v12, null, s15, v12, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_lshlrev_b64_e32 v[12:13], 3, v[11:12] v_subrev_nc_u32_e32 v11, s12, v7 v_add_co_u32 v12, vcc_lo, s6, v12 s_wait_alu depctr_va_vcc(0) s_delay_alu instid0(VALU_DEP_3) v_add_co_ci_u32_e64 v13, null, s7, v13, vcc_lo global_load_b32 v14, v[12:13], off s_wait_loadcnt 0x0 v_cmpx_ge_i32_e64 v11, v14 s_cbranch_execz .LBB2_3 ; %bb.7: ; in Loop: Header=BB2_5 Depth=1 global_load_b32 v12, v[12:13], off offset:4 s_mov_b32 s33, exec_lo s_wait_loadcnt 0x0 v_cmpx_le_i32_e64 v11, v12 s_cbranch_execz .LBB2_2 ; %bb.8: ; in Loop: Header=BB2_5 Depth=1 s_load_b256 s[12:19], s[42:43], 0x10 v_mad_co_i64_i32 v[13:14], null, v8, s10, 0 v_ashrrev_i32_e32 v12, 31, v11 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) v_lshlrev_b64_e32 v[11:12], 2, v[11:12] v_lshlrev_b64_e32 v[13:14], 2, v[13:14] s_wait_kmcnt 0x0 s_lshl_b64 s[12:13], s[12:13], 2 s_wait_alu depctr_sa_sdst(0) s_add_nc_u64 s[12:13], s[28:29], s[12:13] s_wait_alu depctr_sa_sdst(0) v_add_co_u32 v8, vcc_lo, s12, v13 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v13, null, s13, v14, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_co_u32 v11, vcc_lo, v8, v11 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v12, null, v13, v12, vcc_lo s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_add_co_u32 v13, vcc_lo, v11, s40 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v14, null, s41, v12, vcc_lo global_load_b32 v8, v[13:14], off v_add_co_u32 v13, vcc_lo, v11, s30 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v14, null, s31, v12, vcc_lo v_add_co_u32 v15, vcc_lo, v11, s38 s_wait_alu depctr_va_vcc(0) v_add_co_ci_u32_e64 v16, null, s39, v12, vcc_lo s_clause 0x2 global_load_b32 v17, v[13:14], off global_load_b32 v18, v[15:16], off global_load_b32 v19, v[11:12], off v_add_f64_e64 v[13:14], -s[14:15], 1.0 s_wait_loadcnt 0x3 v_cvt_f64_f32_e32 v[11:12], v8 s_wait_loadcnt 0x2 v_cvt_f64_f32_e32 v[15:16], v17 s_wait_loadcnt 0x1 v_cvt_f64_f32_e32 v[17:18], v18 s_wait_loadcnt 0x0 v_cvt_f64_f32_e32 v[19:20], v19 s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) v_mul_f64_e32 v[11:12], s[14:15], v[11:12] v_mul_f64_e32 v[15:16], s[14:15], v[15:16] s_load_b128 s[12:15], s[42:43], 0x30 s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) v_fma_f64 v[11:12], v[13:14], v[17:18], v[11:12] v_add_f64_e64 v[17:18], -s[16:17], 1.0 v_fma_f64 v[13:14], v[13:14], v[19:20], v[15:16] s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_f64_e32 v[11:12], s[16:17], v[11:12] v_fma_f64 v[11:12], v[17:18], v[13:14], v[11:12] s_delay_alu instid0(VALU_DEP_1) v_fma_f64 v[2:3], s[18:19], v[11:12], v[2:3] s_wait_kmcnt 0x0 v_fma_f64 v[4:5], s[12:13], v[11:12], v[4:5] v_fma_f64 v[9:10], s[14:15], v[11:12], v[9:10] s_branch .LBB2_2 .LBB2_9: s_wait_alu depctr_sa_sdst(0) s_or_b32 exec_lo, exec_lo, s3 s_load_b128 s[0:3], s[0:1], 0x40 s_cmp_lg_u32 s27, -1 s_cbranch_scc0 .LBB2_12 ; %bb.10: s_mul_u64 s[4:5], s[20:21], s[20:21] s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_co_u64_u32 v[0:1], null, s4, s27, v[0:1] v_mad_co_u64_u32 v[13:14], null, s5, s27, v[1:2] s_wait_kmcnt 0x0 s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_co_u64_u32 v[11:12], null, v0, 24, s[0:1] v_mad_co_u64_u32 v[12:13], null, v13, 24, v[12:13] s_clause 0x1 global_store_b128 v[11:12], v[2:5], off global_store_b64 v[11:12], v[9:10], off offset:16 s_cbranch_execz .LBB2_13 .LBB2_11: s_endpgm .LBB2_12: s_wait_kmcnt 0x0 .LBB2_13: s_and_saveexec_b32 s0, s23 s_cbranch_execz .LBB2_11 ; %bb.14: v_ashrrev_i32_e32 v8, 31, v7 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mad_co_i64_i32 v[0:1], null, v6, s22, v[7:8] v_mad_co_u64_u32 v[6:7], null, v0, 24, s[2:3] s_delay_alu instid0(VALU_DEP_1) v_mad_co_u64_u32 v[7:8], null, v1, 24, v[7:8] s_clause 0x1 global_load_b128 v[11:14], v[6:7], off global_load_b64 v[15:16], v[6:7], off offset:16 s_wait_loadcnt 0x1 v_add_f64_e32 v[0:1], v[2:3], v[11:12] v_add_f64_e32 v[2:3], v[4:5], v[13:14] s_wait_loadcnt 0x0 v_add_f64_e32 v[4:5], v[9:10], v[15:16] s_clause 0x1 global_store_b128 v[6:7], v[0:3], off global_store_b64 v[6:7], v[4:5], off offset:16 s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_ .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 80 .amdhsa_user_sgpr_count 2 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 21 .amdhsa_next_free_sgpr 44 .amdhsa_reserve_vcc 1 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 1 .amdhsa_inst_pref_size 12 .amdhsa_round_robin_scheduling 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_,"axG",@progbits,_ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_,comdat .Lfunc_end2: .size _ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_, .Lfunc_end2-_ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_ ; -- End function .set _ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_.num_vgpr, 21 .set _ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_.num_agpr, 0 .set _ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_.numbered_sgpr, 44 .set _ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_.num_named_barrier, 0 .set _ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_.private_seg_size, 0 .set _ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_.uses_vcc, 1 .set _ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_.uses_flat_scratch, 0 .set _ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_.has_dyn_sized_stack, 0 .set _ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_.has_recursion, 0 .set _ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_.has_indirect_call, 0 .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 1456 ; TotalNumSgprs: 46 ; NumVgprs: 21 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 2 ; NumSGPRsForWavesPerEU: 46 ; NumVGPRsForWavesPerEU: 21 ; Occupancy: 16 ; WaveLimiterHint : 1 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 2 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .section .text._ZL10tile_mergePKjPK8TileTaskiiiiPKdPd,"axG",@progbits,_ZL10tile_mergePKjPK8TileTaskiiiiPKdPd,comdat .globl _ZL10tile_mergePKjPK8TileTaskiiiiPKdPd ; -- Begin function _ZL10tile_mergePKjPK8TileTaskiiiiPKdPd .p2align 8 .type _ZL10tile_mergePKjPK8TileTaskiiiiPKdPd,@function _ZL10tile_mergePKjPK8TileTaskiiiiPKdPd: ; @_ZL10tile_mergePKjPK8TileTaskiiiiPKdPd ; %bb.0: s_load_b128 s[4:7], s[0:1], 0x10 s_wait_kmcnt 0x0 s_cvt_f32_u32 s2, s5 s_sub_co_i32 s3, 0, s5 s_delay_alu instid0(SALU_CYCLE_2) | instskip(NEXT) | instid1(TRANS32_DEP_1) v_rcp_iflag_f32_e32 v1, s2 v_readfirstlane_b32 s2, v1 s_mul_f32 s2, s2, 0x4f7ffffe s_wait_alu depctr_sa_sdst(0) s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_2) s_cvt_u32_f32 s2, s2 s_wait_alu depctr_sa_sdst(0) s_mul_i32 s3, s3, s2 s_wait_alu depctr_sa_sdst(0) s_mul_hi_u32 s3, s2, s3 s_wait_alu depctr_sa_sdst(0) s_add_co_i32 s2, s2, s3 s_wait_alu depctr_sa_sdst(0) s_mul_hi_u32 s2, ttmp9, s2 s_wait_alu depctr_sa_sdst(0) s_mul_i32 s3, s2, s5 s_add_co_i32 s8, s2, 1 s_wait_alu depctr_sa_sdst(0) s_sub_co_i32 s3, ttmp9, s3 s_wait_alu depctr_sa_sdst(0) s_sub_co_i32 s9, s3, s5 s_cmp_ge_u32 s3, s5 s_cselect_b32 s2, s8, s2 s_cselect_b32 s3, s9, s3 s_wait_alu depctr_sa_sdst(0) s_add_co_i32 s8, s2, 1 s_cmp_ge_u32 s3, s5 s_cselect_b32 s2, s8, s2 s_abs_i32 s3, s4 s_wait_alu depctr_sa_sdst(0) s_cvt_f32_u32 s8, s3 s_sub_co_i32 s9, 0, s3 s_delay_alu instid0(SALU_CYCLE_2) | instskip(NEXT) | instid1(TRANS32_DEP_1) v_rcp_iflag_f32_e32 v1, s8 v_readfirstlane_b32 s8, v1 s_mul_f32 s8, s8, 0x4f7ffffe s_wait_alu depctr_sa_sdst(0) s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_2) s_cvt_u32_f32 s8, s8 s_wait_alu depctr_sa_sdst(0) s_mul_i32 s9, s9, s8 s_wait_alu depctr_sa_sdst(0) s_mul_hi_u32 s9, s8, s9 s_wait_alu depctr_sa_sdst(0) s_add_co_i32 s8, s8, s9 s_wait_alu depctr_sa_sdst(0) v_mul_hi_u32 v1, v0, s8 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v2, v1, s3 v_sub_nc_u32_e32 v2, v0, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) v_subrev_nc_u32_e32 v4, s3, v2 v_cmp_le_u32_e32 vcc_lo, s3, v2 v_dual_cndmask_b32 v2, v2, v4 :: v_dual_add_nc_u32 v3, 1, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_cndmask_b32_e32 v1, v1, v3, vcc_lo v_cmp_le_u32_e32 vcc_lo, s3, v2 s_delay_alu instid0(VALU_DEP_2) v_add_nc_u32_e32 v3, 1, v1 s_mul_i32 s3, s2, s5 s_ashr_i32 s5, s4, 31 s_wait_alu depctr_sa_sdst(0) s_sub_co_i32 s3, ttmp9, s3 s_wait_alu depctr_va_vcc(0) v_cndmask_b32_e32 v1, v1, v3, vcc_lo s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_xor_b32_e32 v1, s5, v1 v_subrev_nc_u32_e32 v1, s5, v1 s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) v_mul_lo_u32 v2, v1, s4 v_sub_nc_u32_e32 v2, v0, v2 s_wait_alu depctr_sa_sdst(0) s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) v_mad_co_u64_u32 v[2:3], null, s3, s4, v[2:3] s_mov_b32 s3, 0 v_mad_co_u64_u32 v[4:5], null, s2, s4, v[1:2] v_cmp_gt_i32_e32 vcc_lo, s6, v2 v_cmp_gt_i32_e64 s2, s7, v4 s_and_b32 s2, vcc_lo, s2 s_wait_alu depctr_sa_sdst(0) s_and_saveexec_b32 s7, s2 s_cbranch_execz .LBB3_6 ; %bb.1: s_load_b128 s[8:11], s[0:1], 0x0 s_mov_b32 s13, s3 s_add_co_i32 s12, ttmp9, 1 s_mov_b32 s2, ttmp9 s_lshl_b64 s[12:13], s[12:13], 2 s_wait_alu depctr_sa_sdst(0) s_lshl_b64 s[2:3], s[2:3], 2 s_wait_kmcnt 0x0 s_add_nc_u64 s[12:13], s[8:9], s[12:13] s_wait_alu depctr_sa_sdst(0) s_add_nc_u64 s[2:3], s[8:9], s[2:3] s_clause 0x1 s_load_b32 s7, s[12:13], 0x0 s_load_b32 s8, s[2:3], 0x0 s_wait_kmcnt 0x0 s_sub_co_i32 s2, s7, s8 s_wait_alu depctr_sa_sdst(0) s_cmp_lt_u32 s2, 2 s_cbranch_scc1 .LBB3_6 ; %bb.2: s_load_b128 s[0:3], s[0:1], 0x20 v_mov_b32_e32 v5, 0 v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0 v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v8, 0 v_mov_b32_e32 v10, 0 s_cmp_le_u32 s7, s8 s_cbranch_scc1 .LBB3_5 ; %bb.3: s_mov_b32 s9, 0 v_mov_b32_e32 v5, 0 s_wait_alu depctr_sa_sdst(0) s_lshl_b64 s[12:13], s[8:9], 4 v_mov_b32_e32 v7, 0 v_mov_b32_e32 v9, 0 v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v6, 0 v_mov_b32_e32 v8, 0 v_mov_b32_e32 v10, 0 s_add_nc_u64 s[10:11], s[10:11], s[12:13] s_mul_u64 s[4:5], s[4:5], s[4:5] s_add_nc_u64 s[10:11], s[10:11], 12 .LBB3_4: ; =>This Inner Loop Header: Depth=1 s_load_b32 s9, s[10:11], 0x0 s_add_co_i32 s8, s8, 1 s_add_nc_u64 s[10:11], s[10:11], 16 s_wait_alu depctr_sa_sdst(0) s_cmp_ge_u32 s8, s7 s_wait_kmcnt 0x0 v_mad_co_u64_u32 v[11:12], null, s4, s9, v[0:1] s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) v_mad_co_u64_u32 v[12:13], null, s5, s9, v[12:13] v_mad_co_u64_u32 v[15:16], null, v11, 24, s[0:1] s_delay_alu instid0(VALU_DEP_1) v_mad_co_u64_u32 v[16:17], null, v12, 24, v[16:17] s_clause 0x1 global_load_b128 v[11:14], v[15:16], off global_load_b64 v[15:16], v[15:16], off offset:16 s_wait_loadcnt 0x1 v_add_f64_e32 v[5:6], v[5:6], v[11:12] v_add_f64_e32 v[9:10], v[9:10], v[13:14] s_wait_loadcnt 0x0 v_add_f64_e32 v[7:8], v[7:8], v[15:16] s_cbranch_scc0 .LBB3_4 .LBB3_5: v_ashrrev_i32_e32 v3, 31, v2 s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) v_mad_co_i64_i32 v[0:1], null, v4, s6, v[2:3] s_wait_kmcnt 0x0 v_mad_co_u64_u32 v[11:12], null, v0, 24, s[2:3] s_delay_alu instid0(VALU_DEP_1) v_mad_co_u64_u32 v[12:13], null, v1, 24, v[12:13] s_clause 0x1 global_load_b128 v[0:3], v[11:12], off global_load_b64 v[13:14], v[11:12], off offset:16 s_wait_loadcnt 0x1 v_add_f64_e32 v[0:1], v[5:6], v[0:1] v_add_f64_e32 v[2:3], v[9:10], v[2:3] s_wait_loadcnt 0x0 v_add_f64_e32 v[4:5], v[7:8], v[13:14] s_clause 0x1 global_store_b128 v[11:12], v[0:3], off global_store_b64 v[11:12], v[4:5], off offset:16 .LBB3_6: s_endpgm .section .rodata,"a",@progbits .p2align 6, 0x0 .amdhsa_kernel _ZL10tile_mergePKjPK8TileTaskiiiiPKdPd .amdhsa_group_segment_fixed_size 0 .amdhsa_private_segment_fixed_size 0 .amdhsa_kernarg_size 48 .amdhsa_user_sgpr_count 2 .amdhsa_user_sgpr_dispatch_ptr 0 .amdhsa_user_sgpr_queue_ptr 0 .amdhsa_user_sgpr_kernarg_segment_ptr 1 .amdhsa_user_sgpr_dispatch_id 0 .amdhsa_user_sgpr_private_segment_size 0 .amdhsa_wavefront_size32 1 .amdhsa_uses_dynamic_stack 0 .amdhsa_enable_private_segment 0 .amdhsa_system_sgpr_workgroup_id_x 1 .amdhsa_system_sgpr_workgroup_id_y 0 .amdhsa_system_sgpr_workgroup_id_z 0 .amdhsa_system_sgpr_workgroup_info 0 .amdhsa_system_vgpr_workitem_id 0 .amdhsa_next_free_vgpr 18 .amdhsa_next_free_sgpr 14 .amdhsa_reserve_vcc 1 .amdhsa_float_round_mode_32 0 .amdhsa_float_round_mode_16_64 0 .amdhsa_float_denorm_mode_32 3 .amdhsa_float_denorm_mode_16_64 3 .amdhsa_fp16_overflow 0 .amdhsa_workgroup_processor_mode 1 .amdhsa_memory_ordered 1 .amdhsa_forward_progress 1 .amdhsa_inst_pref_size 7 .amdhsa_round_robin_scheduling 0 .amdhsa_exception_fp_ieee_invalid_op 0 .amdhsa_exception_fp_denorm_src 0 .amdhsa_exception_fp_ieee_div_zero 0 .amdhsa_exception_fp_ieee_overflow 0 .amdhsa_exception_fp_ieee_underflow 0 .amdhsa_exception_fp_ieee_inexact 0 .amdhsa_exception_int_div_zero 0 .end_amdhsa_kernel .section .text._ZL10tile_mergePKjPK8TileTaskiiiiPKdPd,"axG",@progbits,_ZL10tile_mergePKjPK8TileTaskiiiiPKdPd,comdat .Lfunc_end3: .size _ZL10tile_mergePKjPK8TileTaskiiiiPKdPd, .Lfunc_end3-_ZL10tile_mergePKjPK8TileTaskiiiiPKdPd ; -- End function .set _ZL10tile_mergePKjPK8TileTaskiiiiPKdPd.num_vgpr, 18 .set _ZL10tile_mergePKjPK8TileTaskiiiiPKdPd.num_agpr, 0 .set _ZL10tile_mergePKjPK8TileTaskiiiiPKdPd.numbered_sgpr, 14 .set _ZL10tile_mergePKjPK8TileTaskiiiiPKdPd.num_named_barrier, 0 .set _ZL10tile_mergePKjPK8TileTaskiiiiPKdPd.private_seg_size, 0 .set _ZL10tile_mergePKjPK8TileTaskiiiiPKdPd.uses_vcc, 1 .set _ZL10tile_mergePKjPK8TileTaskiiiiPKdPd.uses_flat_scratch, 0 .set _ZL10tile_mergePKjPK8TileTaskiiiiPKdPd.has_dyn_sized_stack, 0 .set _ZL10tile_mergePKjPK8TileTaskiiiiPKdPd.has_recursion, 0 .set _ZL10tile_mergePKjPK8TileTaskiiiiPKdPd.has_indirect_call, 0 .section .AMDGPU.csdata,"",@progbits ; Kernel info: ; codeLenInByte = 808 ; TotalNumSgprs: 16 ; NumVgprs: 18 ; ScratchSize: 0 ; MemoryBound: 0 ; FloatMode: 240 ; IeeeMode: 1 ; LDSByteSize: 0 bytes/workgroup (compile time only) ; SGPRBlocks: 0 ; VGPRBlocks: 2 ; NumSGPRsForWavesPerEU: 16 ; NumVGPRsForWavesPerEU: 18 ; Occupancy: 16 ; WaveLimiterHint : 1 ; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 ; COMPUTE_PGM_RSRC2:USER_SGPR: 2 ; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 ; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 ; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 ; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 ; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 .section .AMDGPU.gpr_maximums,"",@progbits .set amdgpu.max_num_vgpr, 0 .set amdgpu.max_num_agpr, 0 .set amdgpu.max_num_sgpr, 0 .set amdgpu.max_num_named_barrier, 0 .section .AMDGPU.csdata,"",@progbits .type __hip_cuid_8dd449d3cdcdda82,@object ; @__hip_cuid_8dd449d3cdcdda82 .section .bss,"aw",@nobits .globl __hip_cuid_8dd449d3cdcdda82 __hip_cuid_8dd449d3cdcdda82: .byte 0 ; 0x0 .size __hip_cuid_8dd449d3cdcdda82, 1 .ident "clang version 22.1.8" .section ".note.GNU-stack","",@progbits .addrsig .addrsig_sym __hip_cuid_8dd449d3cdcdda82 .amdgpu_metadata --- amdhsa.kernels: - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 8 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 8 .value_kind: by_value - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .offset: 56 .size: 4 .value_kind: hidden_block_count_x - .offset: 60 .size: 4 .value_kind: hidden_block_count_y - .offset: 64 .size: 4 .value_kind: hidden_block_count_z - .offset: 68 .size: 2 .value_kind: hidden_group_size_x - .offset: 70 .size: 2 .value_kind: hidden_group_size_y - .offset: 72 .size: 2 .value_kind: hidden_group_size_z - .offset: 74 .size: 2 .value_kind: hidden_remainder_x - .offset: 76 .size: 2 .value_kind: hidden_remainder_y - .offset: 78 .size: 2 .value_kind: hidden_remainder_z - .offset: 96 .size: 8 .value_kind: hidden_global_offset_x - .offset: 104 .size: 8 .value_kind: hidden_global_offset_y - .offset: 112 .size: 8 .value_kind: hidden_global_offset_z - .offset: 120 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 312 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd .private_segment_fixed_size: 0 .sgpr_count: 18 .sgpr_spill_count: 0 .symbol: _ZL12splat_kernelPK14PsfCachedEventmiiPKfiidPd.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 62 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .offset: 8 .size: 8 .value_kind: by_value - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 8 .value_kind: by_value - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer - .offset: 48 .size: 4 .value_kind: hidden_block_count_x - .offset: 52 .size: 4 .value_kind: hidden_block_count_y - .offset: 56 .size: 4 .value_kind: hidden_block_count_z - .offset: 60 .size: 2 .value_kind: hidden_group_size_x - .offset: 62 .size: 2 .value_kind: hidden_group_size_y - .offset: 64 .size: 2 .value_kind: hidden_group_size_z - .offset: 66 .size: 2 .value_kind: hidden_remainder_x - .offset: 68 .size: 2 .value_kind: hidden_remainder_y - .offset: 70 .size: 2 .value_kind: hidden_remainder_z - .offset: 88 .size: 8 .value_kind: hidden_global_offset_x - .offset: 96 .size: 8 .value_kind: hidden_global_offset_y - .offset: 104 .size: 8 .value_kind: hidden_global_offset_z - .offset: 112 .size: 2 .value_kind: hidden_grid_dims .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 304 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi .private_segment_fixed_size: 0 .sgpr_count: 14 .sgpr_spill_count: 0 .symbol: _ZL13prepare_tilesPK14PsfCachedEventmiidP8PreparedPi.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 37 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 16 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 24 .size: 8 .value_kind: global_buffer - .offset: 32 .size: 4 .value_kind: by_value - .offset: 36 .size: 4 .value_kind: by_value - .offset: 40 .size: 4 .value_kind: by_value - .offset: 44 .size: 4 .value_kind: by_value - .address_space: global .offset: 48 .size: 8 .value_kind: global_buffer - .offset: 56 .size: 4 .value_kind: by_value - .offset: 60 .size: 4 .value_kind: by_value - .address_space: global .offset: 64 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 72 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 80 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_ .private_segment_fixed_size: 0 .sgpr_count: 46 .sgpr_spill_count: 0 .symbol: _ZL12tile_partialPK8PreparedPKiPKjPK8TileTaskiiiiPKfiiPdSB_.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 21 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 - .args: - .address_space: global .offset: 0 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 8 .size: 8 .value_kind: global_buffer - .offset: 16 .size: 4 .value_kind: by_value - .offset: 20 .size: 4 .value_kind: by_value - .offset: 24 .size: 4 .value_kind: by_value - .offset: 28 .size: 4 .value_kind: by_value - .address_space: global .offset: 32 .size: 8 .value_kind: global_buffer - .address_space: global .offset: 40 .size: 8 .value_kind: global_buffer .group_segment_fixed_size: 0 .kernarg_segment_align: 8 .kernarg_segment_size: 48 .language: OpenCL C .language_version: - 2 - 0 .max_flat_workgroup_size: 1024 .name: _ZL10tile_mergePKjPK8TileTaskiiiiPKdPd .private_segment_fixed_size: 0 .sgpr_count: 16 .sgpr_spill_count: 0 .symbol: _ZL10tile_mergePKjPK8TileTaskiiiiPKdPd.kd .uniform_work_group_size: 1 .uses_dynamic_stack: false .vgpr_count: 18 .vgpr_spill_count: 0 .wavefront_size: 32 .workgroup_processor_mode: 1 amdhsa.target: amdgcn-amd-amdhsa--gfx1201 amdhsa.version: - 1 - 2 ... .end_amdgpu_metadata